Endura RADISYS KP915GV Manual do Utilizador

Endura KP915GV Product Manual www.radisys.com 007-01542-0001 December 2005

KP915GV Product Manual 10 1 Overview Target applications are transaction terminals, medical, test & measurement, gaming, industrial automat

KP915GV Product Manual 100 Item SMBIOS Data Expected Result Slot Length: Other Slot ID: 0004 Slot Characteristics: Provides 3.3V Slot Ch

KP915GV Product Manual 101 Item SMBIOS Data Expected Result Bank Locator Bank 4/5 Memory Type 0Fh(SDRAM) Type Detail 0080h(Synchronous

KP915GV Product Manual 102 Item SMBIOS Data Expected Result 23 Type 127: End-of-Table 4.17 Post Code Technical Description POST Code

KP915GV Product Manual 103 POST Code Description 23h Check validity of RTC value: e.g. a value of 5Ah is an invalid value for RTC minute. Lo

KP915GV Product Manual 104 POST Code Description 75h Detect & install all IDE devices: HDD, LS120, ZIP, CDROM… 77h Detect serial ports &

KP915GV Product Manual 105 5 Customer Support RadiSys Online Support can be found at www.radisys.com and includes device drivers, BIOS update

KP915GV Product Manual 106 A Technical Reference A.1 I/O Map Table 8. I/O Map Address (hex)* Description 0000 – 000F DMA controller 1 0020

KP915GV Product Manual 107 Table 8. I/O Map Address (hex)* Description 1300 – 133F AC97 audio master 1800 – 182F SIO GPIO and control log

KP915GV Product Manual 108 A.3 PCI Device Assignments Table 10. PCI Device Assignments Device IDSEL Bus Number Device Number Function Numb

KP915GV Product Manual 109 A.5 ISA Interrupt Allocation While the motherboard does not include an ISA bus, it includes an ISA-compatible inte

KP915GV Product Manual 11 Product Specification Overview Item Description Network Intel 82573V (or ‘L) PCI-E Gbit Ethernet controller, co-la

KP915GV Product Manual 110 A.7 BIOS Organization The BIOS ROM is a 4or 8Mbit device containing eight or sixteen symmetrical 64KB blocks. The ne

KP915GV Product Manual 111 B Control Registers Notes • The following abbreviations are used in register descriptions: R=Read RO=Read onl

KP915GV Product Manual 112 Prescale 4-bit value to set the watchdog counter period 0..15 16..1s period (a value of 1010b gives a period of 6

KP915GV Product Manual 113 1 Timer is enabled and counting B.5 Watchdog Timeout Period 7 6 5 4 3 2 1 0 Watchdog timeout period R/W R/W R/W

KP915GV Product Manual 114 These bits are input only. Writes to these bits have no effect; reads reflect the state of the GPIO port 2 bits 4 an

KP915GV Product Manual 115 B.10 Controller Part Number The controller part number format is 97-xxyy-0v where v is version number (top 4 bits o

KP915GV Product Manual 116 C Connector Descriptions Note 1: Connector views in the following sections are shown from the motherboard side. Note

KP915GV Product Manual 117 Table 14. Connector part numbers Connector Part Number Type Front Panel Header Foxconn HC11101-L6 2 by 10-way

KP915GV Product Manual 118 Table 15. ADD2 Expansion Slot Pin Signal Pin Signal Pin Signal Pin Signal A27 DVOCD11 B27 DVOCD10 A60 DVOB

KP915GV Product Manual 119 13 Not used but pulled low 14 Not used but pulled high to +5V 15 Not connected C.4 PCI Express x1 Slot Table 17.

KP915GV Product Manual 12 1.2 Motherboard Layout Figure 1 shows the layout of the KP915GV motherboard with the major components identified. Fig

KP915GV Product Manual 120 Table 20. Serial Port Pin SIGNAL Pin SIGNAL 1 DCD 6 DSR 2 SIN 7 RTS 3 SOUT 8 CTS 4 DTR 9 RI 5 GND

KP915GV Product Manual 121 Table 24. 3 x Audio Jack Pin SIGNAL Tip Left Audio Ring Right Audio Sleeve GND Remark L- Line (Line In, Line O

KP915GV Product Manual 122 Table 27. General Purpose I/O Headers Pin SIGNAL Pin SIGNAL 1 GND 2 +5V (fused) 3 PWM 4 GPIO20 5 GPIO21 6

KP915GV Product Manual 123 Table 30. ATA/100 Hard Drive Disk Connector Pin SIGNAL Pin SIGNAL 1 HDRST# 2 GND 3 Device data 7 4 Device

KP915GV Product Manual 124 Table 33. TPM Header Pin SIGNAL Pin SIGNAL 1 LCLK 2 GND 3 LFRAME# 4 KEY PIN 5 LRESET# 6 NC3 7 LAD3

KP915GV Product Manual 125 Table 37. Remote Thermal Sensor Pin SIGNAL 1 DIODE+ 2 DIODE- Table 38. 3 X Fan Connector Pin SIGNAL 1 GND

KP915GV Product Manual 13 Component Identification Description Description Description 1 Super IO 21 Ethernet port 1 (option) 41 USB por

KP915GV Product Manual 14 1.3 Block Diagram Figure 2 shows the block diagram of the KP915GV motherboard. Figure 2. KP915GV Block diagram

KP915GV Product Manual 15 1.4 Configuration The majority of the configuration of the motherboard is done through the Setup utility built int

KP915GV Product Manual 16 Recover Mode (No jumper) With no jumper installed on pins 1, 3, and 5 recovery mode is entered. The motherboard does

KP915GV Product Manual 17 Tamper Switch To make use of the tamper detection logic of the motherboard, connect a momentary switch between pins

KP915GV Product Manual 18 3. Use thumb & forefinger to hold the hook of the load

KP915GV Product Manual 19 Alignment keyPin 1 indicator

KP915GV Product Manual 2 Copyright © 2005 by RadiSys Technology (Ireland) Ltd. All rights reserved. EPC and RadiSys are registered trademarks o

KP915GV Product Manual 20 6. Close the load plate, and slightly push down the tongue side. 7.

KP915GV Product Manual 21 3. The plastic clips at both sides of the DIMM slot will lock automatically. CAUTION Be sure to unplug

KP915GV Product Manual 22 1.5.3 Power Supply In order to avoid damaging any devices, make sure that they have been installed properly

KP915GV Product Manual 23 KP915GV 20-pin ATX power connector: Below is the ATX power supply connector. Make sure that the power supply cabl

KP915GV Product Manual 24 2 Motherboard Description 2.1 Processor Support • Single processor support • Intel® Pentium® 4 Processor 550/551 (3

KP915GV Product Manual 25 2.3 On board Clocking Block Diagram PCI Express x16 SDVOPCI Express/DMI 100 MHz Diff PairUSB/SIO 48 MHzPCI Expre

KP915GV Product Manual 26 Table 1. KP915GV Motherboard Chipset Form Factor PCI-E x16 or ADD2 PCI-E x1 PCI PCI Riser Extension 915GV ATX 1

KP915GV Product Manual 27 • Support for non-ECC memory, unbuffered DIMMs only, in 256MB, 512MB, 1GB, and 2GB sizes, which may be installed a

KP915GV Product Manual 28 Figure 5. KP915GV Board Slot Layout 2.8 Disks • Four 150MB/s SATA ports with locking headers • One Ult

KP915GV Product Manual 29 External Internal Figure 6. Audio Jack Socket and ATAPI Connectors * If a 3 jack external connecto

KP915GV Product Manual 3 Preface Revision History Revision history No. Date Description 1.0 September 2005 • First Release 2.0 December 20

KP915GV Product Manual 30 2.11 I/O • Four USB 2.0 ports on I/O panel via two dual stacked USB over RJ45 connectors • Four USB 2.0 ports on in

KP915GV Product Manual 31 2.15 Programmable Controller (PLD) • Programmable logic device to support configurable system functions • Suppor

KP915GV Product Manual 32 • All configuration is automatic - no stopping on configuration change • Resources freed when unused 2.19 Operating

KP915GV Product Manual 33 2.21 Reliability and Environmental Table 5. Environmental Specifications Characteristic State Value Operating

KP915GV Product Manual 34 2.22 Regulatory Compliance Table 6. Regulatory Testing* Characteristic State Value ESD Operating Designed and t

KP915GV Product Manual 35 3 Specifications 3.1 Product Basis This product based on the Intel® 915GV Express chipset, designed for the Intel®

KP915GV Product Manual 36 • PCI Express endpoint • Independent Bus Master logic for eight general purpose streams: Four input and four output

KP915GV Product Manual 37 • Support for APM-based legacy power management for non-ACPID Desktop implementation • External Glue Integration

KP915GV Product Manual 38 • 5V tolerant buffers on IDE, PCI, and Legacy signals • Integrated 1.5V Voltage Regulator (INTVR) for the Suspend

KP915GV Product Manual 39 • Greater than 100 years Data Retention • Low Power Consumption • Active Read Current: 6 mA (typical) • Stan

KP915GV Product Manual 4 Safety and Approval Notices Safety and approval notices Item Description Battery This product contains a lithiu

KP915GV Product Manual 40 volmuteMUXmute volSD0 STAC9200 Block DiagramAZALIA LINK LOGICPin5Pin8Pin6BIT_CLK Pin11 Pin10SYNCSDIReset# SPDIF

KP915GV Product Manual 41 • Package 48-pin Lead Free LQFP 3.3.2 Hardware Management Interface The LM96000, hardware monitor, has a two wir

KP915GV Product Manual 42 • XOR-tree test mode • Package 24-pin Lead TSSOP 3.3.3 Ethernet Interface Either one or two IEEE 802.3 compatible E

KP915GV Product Manual 43 • Support ASF1.0 and 2.0 alerting • Support Wake On LAN (WOL) and ACPI • Programmable LED functionality • On-c

KP915GV Product Manual 44 • Heceta6-compatible register set accessible via the LPC interface and SMBus • Supports the following combinations

KP915GV Product Manual 45 • Lock option for the configuration and data of each output pin • 15 GPIO ports generate IRQ/SMI/SIOPME# for wake

KP915GV Product Manual 46 • Supports programmable 8-byte sequence “Password” or “Special Keys” for Power Management • Simultaneous recognitio

KP915GV Product Manual 47 • Consumer Remote Control supports RC-5, RC-6, NEC, RCA and RECS 80 • IEEE 1284-compliant Parallel Port • ECP,

KP915GV Product Manual 48 • On-chip Clock Generator: • Generates 48 MHz clock • Generates 32.768 KHz internal clock • VSB3 powered • Based

KP915GV Product Manual 49 KP915GV Item Description Power Supply FSP350-60PLN/350W Current Meter PROVA CM-01 AC/DC Clamp Meter Drives Power

KP915GV Product Manual 5 Contents 1 OVERVIEW ...

KP915GV Product Manual 50 Configuration 2 : Light Load Item Description Memory Micron MT8HF3264AY-40EB3 256MB DDR2-400 CL3 X1 Video On-board

KP915GV Product Manual 51 4 Motherboard BIOS 4.1 BIOS Features • Phoenix Award BIOS • Intel® Pentium® 4 "Prescott" processor in a

KP915GV Product Manual 52 and test progress messages are visible. Pressing the 'TAB' key on the keyboard during a Quietboot switches

KP915GV Product Manual 53 4.3.4 Setup Configuration 4.3.4.1 Standard CMOS Features

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KP915GV Product Manual 57 Note: The Main BIOS level in the figure above is an example only and doesn’t necessarily reflect the latest BIO

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KP915GV Product Manual 6 4 MOTHERBOARD BIOS...51 4.1

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KP915GV Product Manual 63 4.3.4.3 Advanced Chipset Features

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KP915GV Product Manual 65 4.3.4.4 Integrated Peripherals

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KP915GV Product Manual 7 B CONTROL REGISTERS...111 B.

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KP915GV Product Manual 77 4.3.4.5 Power Management Setup

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KP915GV Product Manual 8 Figures Figure 1. KP915GV Board Layout...

KP915GV Product Manual 80 4.3.4.6 PnP/PCI Configurations

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KP915GV Product Manual 83 4.3.4.7 PC Health Status

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KP915GV Product Manual 88 4.3.4.8 Load Default Settings

KP915GV Product Manual 89 4.3.4.9 Set Supervisor Password

KP915GV Product Manual 9 Table 34. Complex Programmable Logic Device (CPLD) JTAG Header...124 Table 35.

KP915GV Product Manual 90 4.3.4.10 Set User Password

KP915GV Product Manual 91 4.3.4.11 Save & Exit Setup

KP915GV Product Manual 92 4.3.4.12 Exit Without Saving

KP915GV Product Manual 93 4.4 Power Management Supports APM and ACPI 2.0 with power states S0, S3, S4 (not S4BIOS), S5 and C0, C1, C2, C3.

KP915GV Product Manual 94 LED State Indicates Blinking yellow The motherboard is in sleep state S1 with a message waiting (as determined by

KP915GV Product Manual 95 4.9.1 Normal Mode This is the factory default position the jumper should be in for normal operation of the motherbo

KP915GV Product Manual 96 NOTE The full-screen logo file must be 640X464 pixels with 16 colors BMP format. 4.12.2 CMOS Default Change The

KP915GV Product Manual 97 4.14 BIOS Flash Usage Map 4.15 Processor Microcode Support IA32 processors have the capability of correcting spe

KP915GV Product Manual 98 Item SMBIOS Data Expected Result BIOS Vendor Phoenix Technologies, LTD BIOS Version 4C7R2BXX Starting Addr Seg E

KP915GV Product Manual 99 Item SMBIOS Data Expected Result System Cache Type Data Associativity Depend on CPU Socket Designation L2-Ca